ACCUMULATORS

Verilog Code for 4-bit Accumulator (Behavioural model):

module accumulator_4bit(

    input [3:0] data_in,

    input clock,

    input reset,

    output reg [3:0] data_out );

always@(posedge clock)

begin

if(reset)

data_out <= 4'b0000;

else

data_out <= data_out + data_in;

end

endmodule

Mathematical Calculation (4-bit accumulator):

clock	reset	data_in (binary)	data_out (binary)
	1	0001	0000
	0	0001	0000
	0	0001	0001
	0	0001	0010
	0	0001	0011
	0	0001	0100
	0	0001	0101
	0	0001	0110

Verilog Code for 8-Bit Accumulator (Behavioural model):

module accumulator_8bit(

    input [7:0] data_in,

    input clock,

    input reset,

    output reg [7:0] data_out

    );

always@(posedge clock)

begin

if(reset)

data_out <= 8'b00000000;

else

data_out <= data_out + data_in;

end

endmodule

Mathematical Calculation (8-bit accumulator):

clock	reset	data_in (binary)	data_out (binary)
	1	00010001	00000000
	0	00010001	00000000
	0	00010001	00010001
	0	00010001	00100010
	0	00010001	00110011
	0	00010001	01000100
	0	00010001	01010101
	0	00010001	01100110

PRBS

Block diagram for 3-bit PRBS:

Verilog code for 3-bit PRBS:

module PRBS_3bit (

    input clk, reset,

    output reg seq_out);

    reg [2:0]p;

    wire s0;

 assign s0 = p[1] ^ p[2];

always @ (posedge clk) begin

if(reset)

begin

   p[0] <= 1;

   p[1] <= 0;

   p[2] <= 0;

   seq_out <= 0;

end

else begin  

   p[0] <= s0;

   p[1] <= p[0];

   p[2] <= p[1];

   seq_out <= p[2];

  end

  end

endmodule 

Block diagram for 4-bit PRBS:

Verilog code for 4-bit PRBS:

module PRBS_4bit (

    input clk, reset,

    output reg seq_out);

reg [3:0]p;

 wire s0;

 assign s0 = p[2] ^ p[3];

 always @ (posedge clk)

begin

  if(reset)

begin

   p[0] <= 1;

   p[1] <= 0;

   p[2] <= 0;

   p[3] <= 0;

   seq_out <= 0;

  end

else begin  

   p[0] <= s0;

   p[1] <= p[0];

   p[2] <= p[1];

   p[3] <= p[2];

   seq_out <= p[3];

  end

end

endmodule

Block diagram for 5-bit PRBS:

Verilog code for 5-bit PRBS:

module PRBS_5bit (

    input clk, reset,

    output reg seq_out);

reg [4:0]p;

 wire s0;

 assign s0 = p[2] ^ p[4];

 always @ (posedge clk)

begin

  if(reset)

begin

   p[0] <= 1;

   p[1] <= 0;

   p[2] <= 0;

   p[3] <= 0;

   p[4] <= 0;

  seq_out <= 0;

  end

else begin  

   p[0] <= s0;

   p[1] <= p[0];

   p[2] <= p[1];

   p[3] <= p[2];

  p[4] <= p[3];

  seq_out <= p[4];

  end

end

endmodule

4 to 1 MUX

Logic diagram for 4 to 1 MUX:

module mux(
    input [3:0] x,
    input [1:0] s,
    output mux_out
    );
     wire a,b,c,d,e,f;
     not g1(a,s[1]);
     not g2(b,s[0]);
     and g3(c,x[0],a,b);
     and g4(d,x[1],a,s[0]);
     and g5(e,x[2],s[1],b);
     and g6(f,x[3],s[1],s[0]);
     or g7(out,c,d,e,f);
endmodule