Flip-Flops (D FF, T FF and JK FF)

D-FF: (Behavioural model)

 
module dff(d,clock,reset,q,qb);

input d,clock,reset;

output reg q,qb;

always@(posedge clock)

begin

case({reset,d})

2'b00 :q=1'b0;

2'b01 :q=1'b1;

default: q=1'b0;

endcase

qb<=~q;

end

endmodule

T-FF: (Behavioural model)

 
module tff(t,clock,reset,q,qb);

input t,clock,reset;

output reg q,qb;

always@(posedge clock)

begin

case({reset,t})

2'b00 :q=q;

2'b01 :q=~q;

default: q=1'b0;

endcase

qb<=~q;

end

endmodule  

Verilog Code for JK-FF: (Behavioural model)

module jkff(j,k,clock,reset,q,qb);

input j,k,clock,reset;

output reg q,qb;

always@(posedge clock)

begin

case({reset,j,k})

3'b100 :q=q;

3'b101 :q=1'b0;

3'b110 :q=1'b1;

3'b111 :q=~q;

default :q=1'b0;

endcase

qb<=~q;

end

endmodule

 

MOD-12 Counter

Block diagram for MOD-12 Counter:

Verilog Code for Modulus counter: (MOD-12 counter)

module mod12_counter(

             input clock,

    input reset,

    output reg [3:0] q );

always@(posedge clock)

begin

if(reset)

q <=4'b0000;

else if(q<=4'b1010)

q <= q+1'b1;

else

q <= 4'b0000;

end

endmodule