|
AND GATE:
module and_gate(
input a,
input b,
output c );
assign c=a&b;
endmodule
|
OR GATE:
module or_gate(
input a,
input b,
output c );
assign c=a | b;
endmodule
|
NOT GATE:
module not_gate(
input a,
output c );
assign c=~a;
endmodule
|
|
NOR GATE:
module nor_gate(
input a,
input b,
output c );
assign c=~(a | b);
endmodule
|
XOR GATE:
module xor_gate(
input a,
input b,
output c );
assign c=a ^ b;
endmodule
|
XNOR GATE:
module xnor_gate(
input a,
input b,
output c );
assign c=~(a ^ b);
endmodule
|
|
NAND GATE:
module and_gate(
input a,
input b,
output c );
assign c=~(a&b);
endmodule
|
Tuesday 2 December 2014
Verilog Code for Basic Logic Gates in Dataflow Modeling
