4 to 1 MUX

Logic diagram for 4 to 1 MUX:

module mux(
    input [3:0] x,
    input [1:0] s,
    output mux_out
    );
     wire a,b,c,d,e,f;
     not g1(a,s[1]);
     not g2(b,s[0]);
     and g3(c,x[0],a,b);
     and g4(d,x[1],a,s[0]);
     and g5(e,x[2],s[1],b);
     and g6(f,x[3],s[1],s[0]);
     or g7(out,c,d,e,f);
endmodule

Flip-Flops (D FF, T FF and JK FF)

D-FF: (Behavioural model)

 
module dff(d,clock,reset,q,qb);

input d,clock,reset;

output reg q,qb;

always@(posedge clock)

begin

case({reset,d})

2'b00 :q=1'b0;

2'b01 :q=1'b1;

default: q=1'b0;

endcase

qb<=~q;

end

endmodule

T-FF: (Behavioural model)

 
module tff(t,clock,reset,q,qb);

input t,clock,reset;

output reg q,qb;

always@(posedge clock)

begin

case({reset,t})

2'b00 :q=q;

2'b01 :q=~q;

default: q=1'b0;

endcase

qb<=~q;

end

endmodule  

Verilog Code for JK-FF: (Behavioural model)

module jkff(j,k,clock,reset,q,qb);

input j,k,clock,reset;

output reg q,qb;

always@(posedge clock)

begin

case({reset,j,k})

3'b100 :q=q;

3'b101 :q=1'b0;

3'b110 :q=1'b1;

3'b111 :q=~q;

default :q=1'b0;

endcase

qb<=~q;

end

endmodule