4-bit Synchronous up counter using T-FF (Structural model)

Circuit Diagram for 4-bit Synchronous up counter using T-FF:

 

Verilog code for tff: (Behavioural model)

module tff(t,clock,reset,q,qb);

input t,clock,reset;

output reg q,qb;

always@(posedge clock)

begin

case({reset,t})

2'b00 :q=q;

2'b01 :q=~q;

default: q=0;

endcase

qb<=~q;

end

endmodule

Verilog Code for 4-bit Synchronous up counter using T-FF (Structural model):

module sync_up(t,clock,reset,q,qb);

input t,clock, reset;

output [3:0]q,qb;

wire x1,x2;

tff T0(t,clock, reset,q[0],qb[0]);

tff T1(q[0],clock, reset,q[1],qb[1]);

and A1(x1,q[0],q[1]);

tff T2(x1,clock, reset,q[2],qb[2]);

and A2(x2,q[2],x1);

tff T3(x2,clock, reset,q[3],qb[3]);

endmodule