1.
When Vgs < Vt
a)
Ids = max, channel width is high
b)
Ids = 0, channel width is high
c)
Ids=0, no channel formation
d)
Ids=min, no channel formation
2.
Condition for Linear region
a)
Vgs = 0, Vds>Vgs-Vt b) Vgs > Vt,
Vds>Vgs-Vt
c)
Vgs < Vt, Vds<Vgs-Vt d) Vgs >Vt,
Vds<Vgs-Vt
3.
Condition for saturation region
a)
Vgs = 0, Vds>Vgs-Vt b) Vgs > Vt,
Vds>Vgs-Vt
c)
Vgs < Vt, Vds<Vgs-Vt d) Vgs >Vt,
Vds<Vgs-Vt
4.
When does MOSFET get pinched-off at drain
a)
Vgs = 0, Vds>Vgs-Vt b) Vgs > Vt,
Vds>Vgs-Vt
c)
Vgs < Vt, Vds<Vgs-Vt d) Vgs >Vt,
Vds<Vgs-Vt
5.
When channel is pinched of then,
a)
Ids increases with Vds b)
Ids independent of Vgs
c)
Ids independent of Vds d)
Ids decreases of Vds
6.
When n-channel depletion type MOSFET are used in enhancement mode
a)
The gate will be positive b)
The gate will be negative
c)
The gate will be at ground level d)
None of the above
7.
If Beta ratio is equal to 1 then threshold voltage, MOSFET Skewed condition is
a)
Vt=VDD/2 , Un-skewed b)
Vt>VDD/2 , Un-skewed
c)
Vt=VDD/2 , Hi-skewed d)
Vt>VDD/2 , Hi-skewed
8. Write the Ids equation for cut-off, Linear and
saturation region
9. To maintain constant gate capacitance when reduce in
length
a) Reduce the Voltage level b) reduce the oxide thickness
c) Increase the depletion layer d) All the above
10. Which one is correct
a) Mobility of electron < Mobility of holes b) Mobility of electron = Mobility of
holes
c) Mobility of electron > Mobility of holes d) Twice the Mobility of electron =
Mobility of holes
11.Reduce in channel length causes
a) Increase in lateral electric field b) Increase in speed of transistor
c) Reduce in power consumption d) All the above
12. Increase in Vds
a) Increases depletion region b) Decreases effective length
c) Increases Ids d)
All the above
13. Threshold voltage varies due to
a) change in Vgs b)
change in Vds c) change in Vsb d) change in Vgd
14. Increasing Temperature causes
a) Reduce in Mobility and Vt b) ON current to decrease
c) OFF current to increase d) All the above
15. At _____________ lateral field strength (Vds/L)
carrier velocity ceases to _______________ linearly with field strength to
obtain velocity saturation.
a) high, reduces b)
low, reduces c) low,
Increases d) High, Increases
16. At _____________ Vertical field strength (Vgs/tox)
carrier scatters more often against the surface and _______________ the carrier
mobility to obtain mobility degradation.
a) high, reduces b)
low, reduces c) low,
Increases d) High, Increases
17. Velocity saturated ON current ______________with
VDD.
a) increases b)
decreases c) Constant d) Undefined
18. Leakage increases exponentially, when Vt
____________ or temperature _____________
a) decreases, Lowers b)
decreases, rises c) increases, lowers d) increases, rises
19. Moore’s Law
states that the transistor count get ______________ for every _________ months.
a) reduces, 8 b)doubled,
8 c) reduces, 18 d) doubled, 18
20. Match the following
a) SSI (SMALL SCALE INTEGRATION) - LESS THAN 1000
GATES
b) MSI (MEDIUM SCALE INTEGRATION) -
LESS THAN 10,000 GATES
c) LSI (LARGE SCALE INTEGRATION) - LESS THAN 10
GATES
d) VLSI (VERY LARGE SCALE INTEGRATION) - GREATER THAN 10,000 GATES
21. Width of Metal 1
a. 1λ b. 2 λ c. 3λ d.4
λ
22. Width of Metal 2
a. 1λ b. 2 λ c. 3λ d.4
λ
23. Width of diffusion
a. 1λ b. 2 λ c. 3λ d.4
λ
24. Width of polysilicon
a. 1λ b. 2 λ c. 3λ d.4
λ
25. Spacing between Metal 1 and Metal 1
a. 1λ b. 2 λ c. 3λ d.4
λ
26. Spacing between Metal 1 and Metal 2
a. 1λ b. 2 λ c. 3λ d.4
λ
27. Spacing between diffusion and diffusion
a. 1λ b. 2 λ c. 3λ d.4
λ
28. Spacing between polysilicon and polysilicon
a. 1λ b. 2 λ c. 3λ d.4
λ
29. Polysilicon overlaps diffusion by
a. 1λ b. 2 λ c. 3λ d.4
λ
30. Polysilicon and contacts have a spacing of
_________ from other polysilicon or contacts
a. 1λ b. 2 λ c. 3λ d.4
λ
31. N-Well surrounds pMOS transistors by _____ and
avoids nMOS transistor by ____.
a. 2 λ, 2 λ b.
3 λ, 3λ c. 6 λ, 6 λ d.12 λ, 12 λ
32. Arranging atoms in single crystal fashion upon
single crystal substrate is
a. Epitaxial growth b.
Oxidation c. Photolithography d. Ion-Implantation
33. The process of growing Sio2 layer above wafer in
vertical direction is
a. Epitaxial growth b.
Oxidation c. Photolithography d. Ion-Implantation
34. Masking of oxide layer with photoresist material
and applying UV rays is the process of _____
a. Epitaxial growth b.
Oxidation c. Photolithography d. Ion-Implantation
35. A technique used to introduce impurities into the
wafer is _______
a. Epitaxial growth b.
Oxidation c. Photolithography d. Ion-Implantation
36. CMOS inverter fabrication using n-Well process
involves
a. P-substrate, n-Well, Polysilicon, n+diffusion,
P+diffusion, contact, Metalization
b. n-substrate, P-Well, Polysilicon, P+diffusion,
n+diffusion, contact, Metalization
c. n-substate, n-well, p-well, polysilicon,
n+diffusion, P+diffusion, contact, Metalization
d. P-substrate, n-well, p-well, polysilicon,
n+diffusion, P+diffusion, contact, Metalization
e. c and d only
37. CMOS inverter fabrication using p-Well process
involves
a. P-substrate, n-Well, Polysilicon, n+diffusion,
P+diffusion, contact, Metalization
b. n-substrate, P-Well, Polysilicon, P+diffusion,
n+diffusion, contact, Metalization
c. n-substate, n-well, p-well, polysilicon,
n+diffusion, P+diffusion, contact, Metalization
d. P-substrate, n-well, p-well, polysilicon,
n+diffusion, P+diffusion, contact, Metalization
e. c and d only
38. Twin-Tub process Involves
a. P-substrate, n-Well, Polysilicon, n+diffusion,
P+diffusion, contact, Metalization
b. n-substrate, P-Well, Polysilicon, P+diffusion,
n+diffusion, contact, Metalization
c. n-substate, n-well, p-well, polysilicon,
n+diffusion, P+diffusion, contact, Metalization
d. P-substrate, n-well, p-well, polysilicon,
n+diffusion, P+diffusion, contact, Metalization
e. c and d only
39. Draw the schematic of
CMOS Inverter
40. Draw the Layout
of CMOS Inverter for unit driven
current.
