ACCUMULATORS

Verilog Code for 4-bit Accumulator (Behavioural model):

module accumulator_4bit(

    input [3:0] data_in,

    input clock,

    input reset,

    output reg [3:0] data_out );

always@(posedge clock)

begin

if(reset)

data_out <= 4'b0000;

else

data_out <= data_out + data_in;

end

endmodule

Mathematical Calculation (4-bit accumulator):

clock	reset	data_in (binary)	data_out (binary)
	1	0001	0000
	0	0001	0000
	0	0001	0001
	0	0001	0010
	0	0001	0011
	0	0001	0100
	0	0001	0101
	0	0001	0110

Verilog Code for 8-Bit Accumulator (Behavioural model):

module accumulator_8bit(

    input [7:0] data_in,

    input clock,

    input reset,

    output reg [7:0] data_out

    );

always@(posedge clock)

begin

if(reset)

data_out <= 8'b00000000;

else

data_out <= data_out + data_in;

end

endmodule

Mathematical Calculation (8-bit accumulator):

clock	reset	data_in (binary)	data_out (binary)
	1	00010001	00000000
	0	00010001	00000000
	0	00010001	00010001
	0	00010001	00100010
	0	00010001	00110011
	0	00010001	01000100
	0	00010001	01010101
	0	00010001	01100110