PRBS

Block diagram for 3-bit PRBS:

Verilog code for 3-bit PRBS:

module PRBS_3bit (

    input clk, reset,

    output reg seq_out);

    reg [2:0]p;

    wire s0;

 assign s0 = p[1] ^ p[2];

always @ (posedge clk) begin

if(reset)

begin

   p[0] <= 1;

   p[1] <= 0;

   p[2] <= 0;

   seq_out <= 0;

end

else begin  

   p[0] <= s0;

   p[1] <= p[0];

   p[2] <= p[1];

   seq_out <= p[2];

  end

  end

endmodule 

Block diagram for 4-bit PRBS:

Verilog code for 4-bit PRBS:

module PRBS_4bit (

    input clk, reset,

    output reg seq_out);

reg [3:0]p;

 wire s0;

 assign s0 = p[2] ^ p[3];

 always @ (posedge clk)

begin

  if(reset)

begin

   p[0] <= 1;

   p[1] <= 0;

   p[2] <= 0;

   p[3] <= 0;

   seq_out <= 0;

  end

else begin  

   p[0] <= s0;

   p[1] <= p[0];

   p[2] <= p[1];

   p[3] <= p[2];

   seq_out <= p[3];

  end

end

endmodule

Block diagram for 5-bit PRBS:

Verilog code for 5-bit PRBS:

module PRBS_5bit (

    input clk, reset,

    output reg seq_out);

reg [4:0]p;

 wire s0;

 assign s0 = p[2] ^ p[4];

 always @ (posedge clk)

begin

  if(reset)

begin

   p[0] <= 1;

   p[1] <= 0;

   p[2] <= 0;

   p[3] <= 0;

   p[4] <= 0;

  seq_out <= 0;

  end

else begin  

   p[0] <= s0;

   p[1] <= p[0];

   p[2] <= p[1];

   p[3] <= p[2];

  p[4] <= p[3];

  seq_out <= p[4];

  end

end

endmodule