VLSI DESIGN
Wednesday, 11 February 2015
2 to 4 Decoder
2 to 4 Decoder (Dataflow Modeling):
module decoder2to4(
input [1:0] a,
output [3:0] d
);
assign d[0]=((~a[1])&(~a[0]));
assign d[1]=((~a[1])&a[0]);
assign d[2]=(a[1]&(~a[0]));
assign d[3]=(a[1]&a[2]);
endmodule
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