Monday 23 February 2015

Johnson Counter / shift counter



Block diagram for Johnson Counter:



Present state
{reset,q}
Next state
q
00000
1000
01000
1100
01100
1110
01110
1111
01111
0111
00111
0011
00011
0001
00001
0000
Default for other values even if reset=1
0000




Verilog code for Johnson Counter / shift counter:
module johnson_counter(
    input clock,
    input reset,
    output reg [3:0] q );
always@(posedge clock)
begin
case ({reset,q})
5'b00000:q=4'b1000;
5'b01000:q=4'b1100;
5'b01100:q=4'b1110;
5'b01110:q=4'b1111;
5'b01111:q=4'b0111;
5'b00111:q=4'b0011;
5'b00011:q=4'b0001;
5'b00001:q=4'b0000;
default:q=4'b0000;
endcase
end
endmodule





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