VLSI DESIGN

Wednesday, 11 February 2015

Simple 2-Bit Multiplication

Verilog code for Simple 2-Bit Multiplication:

module Multiplier(
    input [1:0] a,
    input [1:0] b,
    output [3:0] p );
assign p=a*b;
endmodule

Posted by Unknown at 5:11:00 pm
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Blog Archive

  • ▼  2015 (25)
    • ►  March (2)
    • ▼  February (22)
      • 4 to 1 MUX
      • Flip-Flops (D FF, T FF and JK FF)
      • MOD-12 Counter
      • Decade counter
      • Johnson Counter / shift counter
      • Ring Counter
      • UP/DOWN Counter (Behavioural model)
      • 4-bit Asynchronous up counter using JK-FF (Structu...
      • 4-bit Synchronous up counter using T-FF (Structura...
      • Decimal to BCD Encoder
      • 3 to 8 Decoder
      • 2 to 4 Decoder
      • 4 to 2 Encoder (Structural Modeling)
      • Simple 2-Bit Multiplication
      • 4-Bit Array Multiplier using structural Modeling
      • 8-bit Ripple carry adder using 2 Four bit adder
      • 8-Bit Ripple Carry Adder using Full Adder
      • Design of 4-Bit Ripple Carry Adder Using Full adder
      • Full Adder Using NAND Gate (Structural Modeling):
      • Full Adder using Half Adder (Structural Modeling)
      • Half Subtractor (Dataflow Modeling)
      • Half Adder and Full Adder (Dataflow Modeling)
    • ►  January (1)
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    • ►  December (1)

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