Ring Counter

Block diagram for Ring counter:

 

Verilog code for Ring Counter:

module ring_counter(

    input clock,

    input reset,

    output reg [3:0] q );

always@(posedge clock)

begin

case ({reset,q})

5'b00000:q=4'b1000;

5'b01000:q=4'b0100;

5'b00100:q=4'b0010;

5'b00010:q=4'b0001;

5'b00001:q=4'b1000;

default:q=4'b0000;

endcase

end

endmodule