UP/DOWN Counter (Behavioural model)

Block diagram for UP/DOWN Counter:

 

Verilog code for UP/DOWN Counter: (Behavioural model)

module updown_counter(

    input clock,

    input reset,

             input mode,

    output reg [3:0] q );

always@(posedge clock)

begin

if(reset)

q <=4'b0000;

else if(mode)

q <= q+1'b1;

else

q <= q-1'b1;

end

endmodule